It is desirable that an analog to digital converter should have a good resolution, but also exhibit good linearity. The resolution of a converter is quoted in the number of bits that it converts. Typical high performance converters exhibit 14 or 18 bit resolution. However a user should also pay attention to other performance metrics of the analog to digital converter, such as integral non-linearity, INL, and differential non-linearity, DNL. The differential non-linearity refers to the relative step sizes of each discrete code produced by the analog to digital converter. In an ideal world, if a ramped input voltage is applied to the analog to digital converter then each transition from one digital code to the next should be equally spaced along the analog ramp. However differential non-linearity errors can result in these transitions becoming non-equally spaced. It can be useful to think of the analog values as being sorted into different digital “bins” and therefore each bin should be of the same size. The differential non-linearity can be expressed in terms of size of the least significant bit. It can be seen, using the DNL descriptions shown in FIG. 2, that converters having a differential non-linearity of greater than −1 LSB (−1LSB<DNL error) are guaranteed to have no missing codes. For optimum DC performance DNL error should be zero on all codes.
Although manufacturers take great care to minimise differential non-linearity, process variations and limitations on the physical accuracy to which devices can be fabricated almost inevitably mean that some DNL errors will remain.
U.S. Pat. No. 5,010,339 discloses an arrangement in which a standard analog to digital converter is associated within an additional external circuit which includes a summer preceding the analog to digital converter. The summer receives the signal to be converted at a first input and an output of a digital to analog converter at a second output. The digital to analog converter is driven so as to add a varying but known voltage to the analog signal prior to conversion. This causes repeated input voltage signals of the same value to be converted in different bins of the analog to digital converter thereby minimising DNL errors due to unequal bin widths. However this circuit increases the complexity of the analog to digital converter, and the additional circuitry could be a source of offset errors and gain errors